The video explains the recent announcement by TSMC about their new 1.6 nanometer transistor technology, which involves two major innovations: a new transistor architecture called Nanosheet or gate-all-around (GAA) transistors, and backside power delivery. Here are the key points:
1. Nanosheet/GAA transistors are the next evolution after FinFET transistors, where multiple horizontal transistor channels are stacked vertically, allowing the gate to wrap around the channel from all sides for better control and efficiency.
2. Backside power delivery is a groundbreaking change where the power lines are moved from the front side to the back side of the wafer, freeing up space on the front for signal routing and allowing denser transistor packing.
3. TSMC plans to start producing chips with this technology in 2026, while Intel aims to be the first to market with their 20A process node featuring RibbonFET transistors and backside power delivery, potentially in 2024.
4. Intel’s roadmap is ambitious and risky, introducing two major innovations (RibbonFET and backside power delivery) simultaneously, and their pivotal 14A node in 2027 will rely on expensive new high-NA EUV lithography machines from ASML.
5. The video discusses the economics of chip manufacturing, Moore’s Law, and the challenges Intel faces in making the new technologies cost-effective through techniques like direct self-assembly.
6. Future developments include hyper-NA EUV lithography and the eventual transition to CFET (complementary FET) transistor architecture, which stacks nanosheet transistors vertically.
