Neuromorphic chips // from small edge devices to brain-like supercomputers
Neuromorphic chips can deliver energy savings and shorter latency across a range of applications compared to a traditional CPU, DSP or conventional AI accelerators
Synaptic transistor for neuromorphic computing
The brain’s connectivity is locally dense and globally sparse, forming a small-world graph — a principle prevalent in the evolution of various species, suggesting a universal solution for efficient information routing. However, current artificial neural network circuit architectures do not fully embrace small-world neural network models. Here, we present the neuromorphic Mosaic: a non-von Neumann systolic architecture employing distributed memristors for in-memory computing and in-memory routing, efficiently implementing small-world graph topologies for Spiking Neural Networks (SNNs). We’ve designed, fabricated, and experimentally demonstrated the Mosaic’s building blocks, using integrated memristors with 130 nm CMOS technology. We show that thanks to enforcing locality in the connectivity, routing efficiency of Mosaic is at least one order of magnitude higher than other SNN hardware platforms. This is while Mosaic achieves a competitive accuracy in a variety of edge benchmarks. Mosaic offers a scalable approach for edge systems based on distributed spike-based computing and in-memory routing.
Neuromorphic computing provides alternative hardware architectures with high computational efficiencies and low energy consumption by simulating the working principles of the brain with artificial neurons and synapses as building blocks. This process helps overcome the insurmountable speed barrier and high power consumption from conventional von Neumann computer architectures
Brain-inspired computing systems utilize highly connected artificial neurons and synapses to simulate the physical structures and computing abilities of biological nervous systems. Depending on the computational approach of neurons, popular neural network models can be divided into artificial neural networks (ANNs) and spiking neural networks (SNN). ANNs have been widely used in image classification, speech recognition, etc.
Compared with ANNs, SNNs more closely mimic the working principles of biological neural networks, where the artificial neurons and synapses simulate biological neurons, and synapses represent functionality, structure, and micro-mechanism. Similar to biological neurons, artificial neurons in SNNs produce spikes to encode information during computations.
The two-terminal artificial synapse presents analog switching and is often modeled with a memristor. The multiple conductance states adjusted by consecutive voltage pulses mimic the tunable connection strength (synaptic weight) of biological synapses.
Two-terminal artificial synapses have similar morphologies and structures as biological synapses, and their synaptic performance depends greatly on the ferroelectric nature and domain switching behavior of their ferroelectric layer.
Although FTJ-based memristors exhibit great potential as fundamental synaptic devices, achieving superior learning in high-performance neuromorphic computing remains challenging.
Neuromorphic Analog Signal Processing // NASP
In always-on, at-microphone use cases, NeuroVoice can completely offload neural network processing for voice detection without the use of a microcontroller (MCU) or Digital Signal Processor (DSP).
Menta announces its participation for the first time to the World AI Cannes Festival (WAICF) and will present its adaptive eFPGA approach for accelerating edge artificial intelligence.
Here is a summary of the key points from the paper:
- Artificial neural networks (ANNs) were developed to mimic biological neural networks, with concepts like activation functions inspired by how real neurons work.
- Convolutional neural networks (CNNs) were created based on observations about how visual neurons function, and have been very successful for image classification.
- However, CNNs are limited in processing sequential data like video and speech which have temporal components. Recurrent neural networks (RNNs) were developed to try to address this limitation.
- Transformers were later created as a more efficient alternative to RNNs for sequence modeling tasks like language translation. But transformers still have limitations in very long-range sequence tasks.
- A new class of state-space RNNs has recently shown superior performance to transformers on long-range tasks, but still has drawbacks.
- Temporal Event-based Neural Networks (TENNs) are proposed as a novel architecture combining spatial and temporal convolutions to efficiently process spatiotemporal data.
- TENNs show state-of-the-art accuracy on tasks like speech recognition and time series prediction with orders of magnitude fewer parameters and computations than previous networks.
- TENNs can be trained similarly to CNNs, offering efficient parallelized training. They also offer efficient recurrent operation for deployment at the edge.
- Overall, TENNs offer an innovative and efficient approach to spatiotemporal data processing for advanced edge AI applications.
Dutch chip startup Innatera has introduced the Spiking Neural Processor T1, a neuromorphic microcontroller designed for edge AI sensor applications based on the RISC-V open instruction set architecture. The chip targets low-power edge AI sensor applications and claims to deliver energy savings of up to 500 times with 100 times shorter latency compared to traditional CPUs, DSPs, or conventional AI accelerators. Innatera has addressed software support challenges by developing the Talamo software development kit (SDK) for the Spiking Neural Processor, integrating with the PyTorch machine learning framework. The T1 evaluation kits are available for pre-production trials, with production expected later in the year. The chip has demonstrated applications in radar and audio with a focus on combining analog-mixed signal neuromorphic computing with a RISC-V processor core.
Why neuromorphic? // energy, latency, scalability, etc.
Implementation in FPGA // why not analog devices?
This paper presents an expansion and evaluation of the hardware architecture for the Optimized Deep Event-driven Spiking Neural Network Architecture (ODESA). ODESA is a state-of-the-art, event-driven multi-layer Spiking Neural Network (SNN) architecture that offers an end-to-end, online, and local supervised training method. In previous work, ODESA was successfully implemented on Field-Programmable Gate Array (FPGA) hardware, showcasing its effectiveness in resource-constrained hardware environments. Building upon the previous implementation, this research focuses on optimizing the ODESA network hardware by introducing a novel approach. Specifically, we propose substituting the dot product multipliers in the Neurons with a low-cost shift-register design. This optimization strategy significantly reduces the hardware resources required for implementing a neuron, thereby enabling more complex SNNs to be accommodated within a single FPGA. Additionally, this optimization results in a reduction in power consumption, further enhancing the practicality and efficiency of the hardware implementation. To evaluate the effectiveness of the proposed optimization, extensive experiments and measurements were conducted. The results demonstrate the successful reduction in hardware resource utilization while maintaining the network’s functionality and performance. Moreover, the power consumption reduction contributes to the overall energy efficiency of the hardware implementation.
In this research work, we proposed a new and improved hardware architecture for the ODESA system. By substituting the Neurons’ dot product multipliers with a low-cost shift-register design, we have significantly reduced both the FPGA resources required for implementation and the dynamic power consumption of the system. This design improvement enables more Neurons to be accommodated on a single FPGA, which in turn allows for more complex classification tasks to be performed with less power utilization and at a lower cost on smaller and cheaper FPGAs. Furthermore, our comparison with previous works in this area has shown that our optimized ODESA system outperforms existing systems in terms of both dynamic power consumption and hardware resource utilization. Specifically, we observed a 47% reduction in dynamic power consumption and a 30% reduction in hardware resource utilization. These improvements make the ODESA system even more attractive for implementation in resource-constrained embedded systems, such as those used in robotics, artificial intelligence, and neuroscience. Our work has contributed significantly to the field of spiking neural networks by improving the efficiency and effectiveness of the ODESA system, and our findings are expected to have significant implications for a broad range of applications that rely on embedded systems for their operation.
Neuromorphic supercomputer
Western Sydney University is set to get a new supercomputer by April 2024.
The DeepSouth high-performance computing (HPC) cluster is being provided by the International Centre for Neuromorphic Systems, and will reportedly be capable of 228 trillion “synaptic” operations per second.
The supercomputer has been designed to imitate the workings of a human brain and uses spiking neurons to solve problems.
Neuromorphic technologies work at a different (low) level to construct artificial intelligent systems inspired by the neuroscience and the known nature of the human brain. Traditional computing systems have an external memory based computing architecture that very inefficient to simulate a brain-like systems, while neuromorphic chips are designed to mimic the natural structure of the brain as closely as possible (digital neural network).
But we don’t know how actually brain and human intelligence work, all current models are based on some ideas and hypotheses.
Artificial intelligence is a transformative branch of computer science that focuses on creating systems capable of performing tasks that typically require human intelligence, encompassing abilities such as learning, reasoning, problem-solving, perception, and language understanding.
Although the sector has witnessed significant growth since its inception, its development faces multiple challenges, such as:
Computational power limitations,
Data transfer bottlenecks in von Neumann architecture,
Scalability issues.
Neuromorphic computing mitigates these issues.
Don’t forget about economics. Design of new hardware chips/systems is very expensive in comparison to traditional mass production computing devices. Here it is a multidimensional problem (scalability, energy, latency, cost-of-design, cost-of-production, cost-of-use, cost-of-programming, cost-of-support).
